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| MCF5307 UART MODULE 5307 UART Module Motorola ColdFire (R) 1- 1 UART INTERFACE OVERVIEW * TWO INDEPENDENT, FULL DUPLEX ASYNCHRONOUS/SYNCHRONOUS RECEIVER/ TRANSMITTER CHANNELS * INDEPENDENTLY PROGRAMMABLE BAUD RATE GENERATOR FOR EACH RECEIVER AND TRANSMITTER DERIVABLE FROM SYSTEM CLOCK OR EXTERNAL CLOCK ON TIN PIN * PROGRAMMABLE DATA FORMAT, FIVE TO EIGHT DATA BITS PLUS PARITY OR ADDRESS MARK BIT PARITY OPTIONS: 1- ODD PARITY 2- EVEN PARITY 3- FORCE PARITY 4- NO PARITY MCF5307 I Addr Gen I Fetch1 I Fetch2 I Decode Instr Buf Dec&Sel Op 8K Unified Cache System Bus Controller * PROGRAMMABLE CHANNEL MODES NORMAL (FULL DUPLEX) AUTOMATIC ECHO (HALF DUPLEX) LOCAL LOOPBACK REMOTE LOOPBACK *UART CAN BE PROGRAMMED TO DIRECTLY INTERRUPT DMA FOR FAST TRANSFERS 4K SRAM 2 UARTs 2 Timers 4 DMA A Gen & Ex DRAM Cntr & Chip Selects Interrupt Ctr General Purpose I/O MAC Debug Rev B Module JTAG PLL M-Bus 5307 UART Module Motorola ColdFire (R) 1- 2 UART RECEIVER FEATURES : * AUTOMATIC WAKEUP FOR MULTIDROP APPLICATIONS * FRAMING, PARITY AND OVERRUN ERROR DETECTIONS * FALSE START BIT DETECTION * LINE-BREAK DETECTION * DETECTION OF A BREAK ORIGINATING IN THE MIDDLE OF A CHARACTER * START/END BREAK INTERRUPT /STATUS * FOUR STAGE FIFO RECEIVE BUFFER * RECEIVER OPERATION MAY BE POLLED OR INTERRUPT DRIVEN 5307 UART Module Motorola ColdFire (R) 1- 3 UART TRANSMITTER FEATURES: * DOUBLE-BUFFERED OPERATION * PARITY GENERATION: ODD, EVEN, NO PARITY OR FORCE PARITY * STOP BIT GENERATION FROM .563 TO 2-BITS * BREAK GENERATION * AUTOMATIC NEGATION OF REQUEST-TO-SEND UPON COMPLETION OF MESSAGE TRANSMISSION * PROGRAMMABLE CHARACTER LENGTH FROM 5 TO 8-BITS 5307 UART Module Motorola ColdFire (R) 1- 4 UART BLOCK DIAGRAM AND INTERFACE SIGNALS RxD - SERIAL RECEIVE DATA PIN, DATA IS SAMPLED ON RISING EDGE OF CLOCK SOURCE. 4-CHAR REC_BUFF RxD TxD - SERIAL TRANSMIT DATA PIN, DATA IS SHIFTED OUT ON FALLING EDGE OF CLOCK SOURCE. RTS - REQUEST-TO-SEND, THIS PIN MAY BE USED TO CONTROL SERIAL DATA FLOW WHEN CONNECTED TO CTS INPUT PIN OF THE TRANSMITTER. CTS - CLEAR-TO-SEND, THIS SIGNAL GENERATES INTERRUPT REQUEST TO THE CPU UPON CHANGE OF STATE. SYS_CLK - CLOCK INPUT TO BAUD RATE GENERATOR OR 16-BIT TIMER TO GENERATE STANDARD BAUD RATES. IRQ - AN INTERNAL INTERRUPT REQUEST SIGNAL FROM THE DUART INTERFACE. TIN - CAN BE USED AS THE CLOCK SOURCE SYS_CLK INTERNAL DATA_BUS 2-CHAR TX_BUFF TxD INPUT PORT CTS IRQ OUTPUT PORT RTS 16-BIT TIMER/ BAUD RATE GENERATOR TIN 5307 UART Module Motorola ColdFire (R) 1- 5 BUFFERED DUART (Rx/Tx Buff) TRANSMIT BUFFER 1, 2 TxD DATA BUS TRANSMIT SHIFT REGISTER TRANSMIT HOLDING REGISTER (WRITE ONLY) TxRDY - TRANSMITTER READY FOR A CHAR TO BE WRITTEN INTO HOLDING REGISTER. TxEMP - TRANSMIT SHIFT REGISTER IS EMPTY. DATA BUS RECEIVE BUFFER 1, 2 RECEIVE HOLDING REGISTER 1 RECEIVE HOLDING REGISTER 2 RECEIVE HOLDING REGISTER 3 RECEIVER SHIFT REGISTER RxRDY - RECEIVER READY 1 OR MORE CHAR IN FIFO. (READ ONLY) RxD FFULL - FIFO full at 3 bytes. 5307 UART Module Motorola ColdFire (R) 1- 6 RECEIVER REGISTERS UMR1 - UART MODE REGISTER 1 RxRTS RxIRQ RST: 0 0 ERR 0 PM1 0 PM0 0 PT 0 B/C1 0 B/C0 READ/WRITE 0 BITS/CHAR PARITY MODE AND TYPE ERROR MODE 000 - EVEN PARITY 001 - ODD PARITY 010 - LOW PARITY 011 - HIGH PARITY 10x - NO PARITY 110 - MULTIDROP MODE / DATA CHAR 111 - MULTIDROP MODE / ADDRESS CHAR 00 - FIVE BITS 01 - SIX BITS 10 - SEVEN BITS 11 - EIGHT BITS 1 - BLOCK MODE 0 - CHARACTER MODE RECEIVER READY SELECT 1 - FFULL IS THE SOURCE THAT GENERATES IRQ 0 - RxRDY IS THE SOURCE THAT GENERATES IRQ RXVR RTS CONTROL 1 - UPON RECEIPT OF A START BIT, RTS IS NEGATED IF THE CHANNEL'S FIFO IS FULL 0 - RECEIVER HAS NO EFFECT ON RTS 5307 UART Module Motorola ColdFire (R) 1- 7 UART REGISTERS UMR2 - UART MODE REGISTER 2 CM1 RST: 0 CM0 0 TxRTS 0 TxCTS 0 SB3 0 SB2 0 SB1 0 SB0 READ/WRITE 0 STOP BIT LENGTH CONTROL REFER TO USER'S MANUAL FOR STOP BIT LENGTH TRANSMITTER CLEAR-TO-SEND 1 = TRANSMITTER USES CTS TO CONTROL SERIAL DATA FLOW 0 = CTS HAS NO EFFECT ON TRANSMITTER TRANSMITTER READY-TO-SEND 1 = NEGATE RTS 1-BIT TIME AFTER THE LAST BIT OF LAST CHARACTER HAS BEEN TRANSMITTED 0 = TRANSMITTER HAS NO EFFECT ON RTS CHANNEL MODE 0 0 = NORMAL OPERATION 0 1 = AUTOMATIC ECHO 1 0 = LOCAL LOOPBACK 1 1 = REMOTE LOOPBACK 5307 UART Module Motorola ColdFire (R) 1- 8 UART MODES TRANSMITTER DISABLED TRANSMITTER TxD C P U RECEIVER RxD C P U -------- TRANSMITTER ----- TxD RECEIVER RxD NORMAL OPERATION UMR2(CM1:0) = 00 AUTOMATIC ECHO UMR2(CM1:0) = 01 TRANSMITTER DISABLED - - - - - - - TRANSMITTER - - - - TRANSMITTER ----- TxD OUTPUT C P U RECEIVER ----- TxD DISABLED C P U - - - - - - - RECEIVER RxD ----RECEIVER DISABLED INPUT RxD DISABLED LOCAL LOOPBACK UMR2(CM1:0) = 10 5307 UART Module REMOTE LOOPBACK UMR2(CM1:0) = 11 Motorola ColdFire (R) 1- 9 RECEIVER/TRANSMITTER STATUS USR - STATUS REGISTER RB RST: 0 FE 0 PE 0 OE 0 TxEMP 0 TxRDY 0 FFULL 0 RxRDY 0 READ ONLY RECEIVER READY 1 = 1 OR MORE CHARACTERS ARE WAITING TO BE READ 0 = CPU READ THE ENTIRE FIFO FIFO IS FULL 1 = 3-STAGE RECEIVE BUFFER IS FULL 0 = FIFO IS NOT FULL AND MAY CONTAIN UP TO 2-CHAR TRANSMITTER READY 1 = TRANSMIT HOLDING REGISTER IS EMPTY 0 = TRANSMITTER IS FULL OR DISABLED TRANSMITTER EMPTY 1 = UNDERRUN CONDITION IS DETECTED 0 = TRANSMITTER IS NOT EMPTY OR DISABLED OVERRUN ERROR 1 = ONE OR MORE CHARS IN THE DATA STREAM HAS BEEN LOST 0 = NO OVERRUN CONDITION PARITY ERROR 1 = PARITY ERROR 0 = NO PARITY ERROR ( IN MULTIDROP MODE, THIS BIT STORES THE VALUE OF THE A/D BIT) FRAMING ERROR 1 = NO STOP BIT WAS DETECTED WHEN CHAR WAS RECEIVED IN THE FIFO. 0 = NO FRAMING ERROR WAS DETECTED RECEIVED BREAK 1 = A BREAK CHAR HAS BEEN RECEIVED AND FURTHER ENTRIES TO THE FIFO ARE INHIBITED UNTIL RxD RETURNS TO THE HIGH STATE FOR AT LEAST ONE-HALF BIT TIME. 0 = NO BREAK RECEIVED 5307 UART Module Motorola ColdFire (R) 1- 10 BAUD RATE SELECTION UCSR - CLOCK SELECT REGISTER RCS3 RST: 1 RCS2 1 RCS1 0 RCS0 1 TCS3 1 TCS2 1 TCS1 0 TCS0 1 WRITE ONLY 1101 1110 1111 TIMER X16 CLK X1 CLK 1101 1110 1111 TIMER X16 CLK X1 CLK RECEIVER BAUD RATE SELECTION TRANSMITTER BAUD RATE SELECTION 5307 UART Module Motorola ColdFire (R) 1- 11 UART COMMANDS UCR - COMMAND REGISTER RST: 0 WRITE ONLY MISC2 0 MISC1 0 MISC0 0 TC1 0 TC0 0 RC1 0 RC0 0 MISC2 MISC1 MISC0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 COMMAND NO COMMAND RESET MODE REG PNTR RESET RECEIVER RESET TRANSMITTER RESET ERROR STATUS RESET BRK CHANGE IRQ START BREAK STOP BREAK TC1 0 0 1 1 TC0 0 1 0 1 COMMAND NO COMMAND ENABLE TRANSMITTER DISABLE TRANSMITTER DO NOT USE TRANSMITTER COMMANDS MISC COMMANDS RC1 0 0 1 1 RC0 0 1 0 1 COMMAND NO COMMAND ENABLE RECEIVER DISABLE RECEIVER DO NOT USE RECEIVER COMMANDS 5307 UART Module Motorola ColdFire (R) 1- 12 UART REGISTERS UIPCR - INPUT PORT CHANGE REGISTER 0 RST: 0 0 0 0 0 COS 0 1 0 1 1 1 1 CTS CTS READ ONLY COS - WHEN SET INDICATES A LOW-TO-HIGH OR HIGH-TO-LOW TRANSITION LONGER THAN 25-50usec HAS OCCURRED ON INPUT PIN. AN IRQ IS GENERATED TO THE CPU, IF ENABLED CTS - INDICATES THE CURRENT PIN STATE INPUT UIP - INPUT PORT REGISTER RST: 1 1 1 1 1 1 1 CTS READ ONLY CTS CTS - INDICATES THE CURRENT PIN STATE INPUT UACR - AUXILIARY CONTROL REGISTER BGR RST: 0 CTMS2 CTMS1 CTMS0 0 0 0 0 0 0 IEC 0 WRITE ONLY BGR=1, SET 2 OF BAUD RATES IS SELECTED BGR=0, SET 1 OF BAUD RATES IS SELECTED CTMS[2:0} SHOULD BE SET TO 110 IEC = 1, ENABLE IRQ TO CPU BY A CHANGE OF STATE ON CTS INPUT. IEC = 0, NO IRQ IS GENERATED TO CPU BECAUSE OF A CHANGE ON CTS 5307 UART Module Motorola ColdFire (R) 1- 13 UART REGISTERS UOP1 - OUTPUT PORT DATA REGISTER RST: RTS 0 WRITE ONLY BIT SET Write a 1 to force RTS low UOP0 - OUTPUT PORT DATA REGISTER RST: RTS - WRITE ONLY BIT RESET Write a 1 to force RTS high 5307 UART Module Motorola ColdFire (R) 1- 14 INTERRUPT ENABLE & STATUS UISR - INTERRUPT STATUS REGISTER COS RST: 0 0 0 0 0 DB 0 RxRDY 0 TxRDY 0 READ ONLY UIMR - INTERRUPT MASK REGISTER COS RST: 0 0 0 0 0 DB 0 RxRDY 0 TxRDY 0 WRITE ONLY TRANSMITTER READY 1 = TRANSMIT HOLDING REGISTER IS EMPTY 0 = CPU LOADED TRANSMIT REG. CHANGE OF STATE 1 = INPUT PIN CHANGED STATE 0 = NO CHANGE OF STATE RECEIVER READY OR FIFO FULL. DUPLICATE OF UMR1 BIT6 DELTA BREAK 1 = RECEIVER DETECTED BREAK 0 = NO BREAK DETECTED 5307 UART Module Motorola ColdFire (R) 1- 15 UART INTERRUPT CONTROL ICR 3 & 4- UART INTERRUPT CONTROL REGISTER 3 & 4 B7.........................................................................................................B0 READ/WRITE AVEC - - IL2 IL1 IL0 IP1 IP0 INTERRUPT LEVEL 1 1 1 = IRQ SOURCE HAS HIGHEST PRIORITY 0 0 1 = IRQ SOURCE HAS LOWEST PRIORITY 0 0 0 = NO INTERRUPT IS REQUESTED AUTOVECTOR 0 - IRQ SOURCE RETURNS VECTOR 1 - SIM GENERATES AVEC FOR IRQ SOURCE INTERRUPT PRIORITY 1 1 = HIGHEST 0 0 = LOWEST UIVR - INTERRUPT VECTOR REGISTER READ/WRITE IVR7 RST: 0 IVR6 0 IVR5 0 IVR4 0 IVR3 1 IVR2 1 IVR1 1 IVR0 1 5307 UART Module Motorola ColdFire (R) 1- 16 |
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